Cartesian Routing Progress to Date and Future Directions

Existing hierarchical routing schemes, employing distance vector and link state routing algorithms, require the exchange of routing information for the construction and maintenance of routing tables [1]. As networks increase in size, the memory requirements for the routing tables and the time taken to search the tables increase proportionally [11]. Further, as the popularity of computer networks increases, the size of the address space can become a limiting factor [9]. Although many Internet routers employ specialized caches to hold recently-used addresses, table search times can degenerate to O(log(n)) and O(n), for ordered and unordered tables, respectively [2, 10]. Furthermore, routers become the bottleneck in high-speed optical networks since packets must be converted from the network's media (light) to the router's media (electrical). In this paper, the authors discuss a novel packet routing technology known as Cartesian routing that is applicable to both small and large scale networks [7]. Cartesian routing di ers from existing provider-based unicast routing in that routers maintain a minimal amount of state information. Routing tables are unnecessary since communications are topologically dependent, potentially reducing router and network overheads. Routing decisions which can take O(log(n)) to O(n) time using routing tables are reduced to O(1) time in Cartesian routing. The paper describes the fundamental Cartesian routing algorithm, its topological and addressing requirements, and its recursive implementation for global internetworks. The paper also presents a description of a Cartesian network simulation tool, as well as a prototype Cartesian router. Finally, the paper examines potential future research areas including the design of optical Cartesian routers, improved fault tolerance, network interconnection, and some of the issues surrounding possible designs of Cartesian Internets. Author to whom correspondence should be addressed. yFaculty of Computer Science, Dalhousie University. 1 Cartesian Routing and Cartesian Networks The fundamental principles of Cartesian routing can be illustrated using a linear routing algorithm in an one-dimensional network topology [5, 6]. In this topology, each router is associated with two `side' ports (east and west), allowing it to connect to, at most, two other routers. Every router is bound to a unique address and maintains no state information other than this address. Linear routing is achieved in the network by imposing an ordering on the routers which is based upon the unique router addresses; for example, west-to-east in ascending order (unless otherwise speci ed, west is always considered `less than' east). When a packet is to be transmitted on the network, the transmitting router's layer 3 determines the packet's initial direction by examining the destination address. If this is less than the router's address, the packet is queued for transmission on the west port, otherwise on the east port. When a packet arrives at a router, its address is compared with the router's address: if the addresses are the same, the packet can be kept; if the packet arrived from the east (west) and is greater than (less than) the router's address, it is discarded; otherwise the packet is forwarded out the opposite port from which it arrived. A Cartesian network consists of a set of collectors and one or more arterials, as shown in Figure 1. Each collector is a chain of collector routers running east-west, sharing a common latitude. Collector routers have two ports (east and west) to exchange packets \horizontally". Each collector router also has a bottom port which allows it to connect to a set of local hosts. Arterials exchange packets between collectors. Each arterial router, except the most northerly and the most southerly, has, at least, four ports (north, south, east and west). Arterials need not share a common longitude. Collector and collector routers Virtual arterial Arterial and arterial routers Figure 1: A Cartesian Network In a Cartesian network, the imposed topological structure relieves each router from maintaining routing tables. Each router is bound to a unique address (for example, a latitude and longitude). Both collector and arterial routers implement the linear routing algorithm: collector routers examine latitudes while arterial routers examine longitudes. The state information maintained is minimal: each router maintains an Arterial Direction Indicator (ADI) that indicates which of its latitudinal ports leads to an arterial and whether the arterial connects to the north, south, or both. A router's ADI is updated when an arterial router sends an Arterial This Way (ATW) message out its collector ports or when a router detects a change in the state of its links. An arterial router di ers slightly from a collector router in that it can have multiple links leading to other arterials, for both fault tolerance (should an arterial link fail) and potential shortcutting. A virtual arterial is a collector that doubles as an arterial, allowing a continuous path from north-to-south, as shown in Figure 1. A detailed description of Cartesian routing can be found in [7]. 1.1 Progress to Date 1.1.1 Prototype Collector Router Implementation A prototype multiprocessor collector router has been developed for demonstration purposes [4]; the router supports three full-duplex RS-232 ports (bottom, east, and west). Each port is controlled by an Atmel AT90LS8535 RISC microprocessor with a built-in UART and a 486 byte bu er. Each microprocessor is associated with a 1 kilobyte FIFO (to hold packets queued for output) and two tri-state octal bu ers (controlling access to the FIFOs of the other microprocessors). The 128-bit address of the router is stored in each microprocessor. When a packet starts to arrive at a port, the microprocessor compares the destination address with the router's address to determine the output port. If the packet is not to be discarded, the microprocessor writes